1. Field of the Invention
The present invention relates to a Group III-N high electron mobility transistor (HEMT) and, more particularly, to a Group III-N HEMT with a floating substrate region and a grounded substrate region.
2. Description of the Related Art
Group III-N high electron mobility transistors (HEMTs) have shown potential superiority for power electronics due to their wider bandgap and better electron transport properties. These material properties translate into high breakdown voltage, low on-resistance, and fast switching. Group III-N HEMTs can also operate at higher temperatures than silicon-based transistors. These properties make group III-N HEMTs well suited for high-efficiency power regulation applications, such as lighting and vehicular control.
FIG. 1 shows a cross-sectional view that illustrates a conventional group III-N HEMT 100. As shown in FIG. 1, group III-N HEMT 100 includes a substrate 110, and a layered region 112 that is formed on the top surface of the substrate 110. The layered region 112, in turn, includes a barrier layer 114 at the top, a channel layer 116 in the middle, and a buffer layer 118 at the bottom that lies between the substrate 110 and the channel layer 116. The barrier layer 114, the channel layer 116, and the buffer layer 118 are each typically implemented with one or more sequential group-III nitride layers, with the group-III including one or more of In, Ga, and Al. The barrier layer 114 is commonly formed from AlGaN, and the channel layer 116 is commonly formed from GaN.
As discussed in Mishra et al., “AlGaN/GaN HEMTs—An Overview of Device Operation and Applications”, Proceedings of the IEEE, Vol. 90, No. 6, June 2002, pp. 1022-1031, the channel layer and the barrier layer of an HEMT have different polarization properties and band gaps that induce the formation of a two-dimensional electron gas (2DEG) that lies at the top of the channel layer. The 2DEG, which has a high concentration of electrons, is similar to the channel in a conventional field effect transistor (FET). These electrons move at a comparatively higher speed than in a silicon MOSFET due to the characteristic high mobility of the material combined with the absence of undesirable collisions with dopant impurities.
Native group III-N substrates are not easily available, so the layered region 112 is conventionally grown on the substrate 110 using epitaxial deposition techniques such as metal organic chemical vapor deposition (MOCVD) and molecular beam epitaxy (MBE). The buffer layer 118 provides a transition layer between the substrate 110 and the channel layer 116 in order to address the difference in lattice constant and to provide a dislocation-minimized growing surface.
The substrate 110 is commonly implemented with SiC because SiC has a reasonably low lattice mismatch (˜3%) and a high thermal conductivity. SiC substrates, however, are expensive and limited in size. The substrate 110 is also commonly implemented with Si due to the low cost of Si and access to Si processing infrastructure. Si substrates, however, limit the thickness of the buffer layer 118 to 2-3 um on a 6-inch substrate due to the stress and subsequent bowing of the wafer.
One of the limitations of a 2-3 um buffer thickness is that a thin buffer layer places a limit on the breakdown voltage of the device. For instance, a 2 um thick buffer breaks down at 300V. One approach to increasing the buffer breakdown voltage is to float the substrate. By floating the substrate, the buffer breakdown voltage from drain to source is doubled to 600V because the voltage is supported by two buffer layer thicknesses.
For example, as shown in FIG. 1, when a Si substrate is floated and the drain-to-source breaks down, the breakdown current follows a path from the drain to the source that includes the breakdown path segments A, B, and C. The breakdown path segments A and C each have a breakdown voltage of approximately 300V, whereas the breakdown path segment B is ohmic. Thus, in order to achieve the full breakdown voltage (600V), the substrate 110 must be able to float up to half the breakdown voltage (300V).
However, the requirement for a floating substrate causes a major issue for packaging. If a conventional package is used, the group III-N HEMT is attached using a non-conductive epoxy. Non-conductive epoxies, however, have worse thermal conductivity than conductive epoxies. This will cause a serious problem, since the group III-N device is intended for power applications, and needs to have a good heat sink. There are packages with improved heat sinking, which use an intermediate insulating layer with high thermal conductivity like AlN. However, these are expensive and still have lower thermal conductivity than direct-attach with a conductive epoxy.
In addition to packaging, the requirement for a floating substrate also has several other issues. A floating substrate can cause crosstalk from capacitive coupling between adjacent devices. In addition, if the floating voltage changes rapidly, EMI radiation is a concern. Further, the voltage of a floating substrate is not controlled, since the substrate is not directly contacted. Unregulated voltages are not desirable in circuit design. Thus, there is a need for alternate approaches to forming group III-N HEMTs.